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The
Actel IGLOO
®
nano
and
ProASIC
®
3 nano Flash FPGA
s raise the bar on performance, price, power consumption, and compact size. The
Actel
IGLOO nano FPGA
is the industry's lowest power, as low as 2µW, and smallest size
FPGA
series. The
IGLOO nano
comes in small footprint packages as small as 3x3 mm and is supported by Flash * Freeze Technology that enables ultra-low power for portable applications. The
Actel ProASIC3
nano FPGA
also delivers high performance, low-power consumption, and enhanced I/O functionality. The
ProASIC3 nano
and
IGLOO nano
are designed specifically for high-volume, cost-sensitive industrial, medical, and consumer applications.
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IGLOO nano FPGAs
Actel IGLOO®
nano FPGAs offer groundbreaking possibilities in power, size, lead-times, operating temperature, and cost. Available in logic densities from 10,000 to 250,000 gates, the 1.2 V to 1.5 V
IGLOO nano
devices have been designed for high-volume applications where power and size are key decision criteria. Priced competitively in the market,
IGLOO nano
devices are perfect ASIC or ASSP replacements, yet retain the historical
FPGA
advantages of flexibility and quick time-to-market in low-power and small footprint profiles.
Key Features
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Ultra-low power in Flash*Freeze mode, as low as 2 µW
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Variety of small footprint packages as small as 3x3 mm
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Zero lead time on selected devices
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Known good die supported
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Enhanced commercial temperature
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Reprogrammable flash technology
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1.2 V to 1.5 V single voltage operation
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Enhanced I/O features
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Clock conditioning circuits (CCCs) and PLLs
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Embedded SRAM and nonvolatile memory (NVM)
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In-system programming (ISP) and security
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ProASIC3 nano FPGAs
Actel ProASIC®
3 nano FPGAs bring a new level of value and flexibility to high volume markets. When measured against the typical project metrics of performance, cost, flexibility and time to market, the
ProASIC3 nano
devices provide an attractive alternative to ASICs and application-specific standard products (ASSPs) in fast moving or highly competitive markets. Customer driven total system cost reduction was a key design criteria for the
ProASIC3 nano
program. Reduced device cost, availability of Known Good Die, a single chip implementation, and a broad selection of small-footprint packages, all contribute to lower total system costs.
Key Features
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Lowest cost
FPGA
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Wide selection of low cost, small footprint packages
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Known good die program
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Enhanced commercial temperature range
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Zero lead time on selected devices
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Selectable Schmitt trigger inputs
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Hot-swappable and cold-sparing I/Os
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Cost-optimized, reprogrammable, and nonvolatile
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1,024 bits of user flash memory
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Single-chip and live at power-up
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In-system programming (ISP) and security
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